1. Technical Field
The present invention generally relates to logic gates, and more particularly to static logic gates with low power consumption and short evaluation times.
2. Description of the Related Art
Logic circuits, particularly those used to simultaneously evaluate an equation with a large number of inputs have been implemented in a variety of architectures. Among static logic gates, which require no preset signals and maintain their output state as long as the input signals remain in the same state, two standard architectures are well known in Metal-Oxide-Semiconductor (MOS) implementations.
In order to evaluate an OR equation, as shown in FIG. 1A, ladders of PMOS transistors (with each gate coupled to a logic input and the bottom of the ladder connected to ground) are stacked in series so that if any logic input is high, the ladder will not conduct and therefore produce a logic high output at the top of the ladder. In order to evaluate an AND equation, a similar ladder can be formed by NMOS transistors, as shown in FIG. 1B so that if any gate is low, the ladder will not conduct, producing a high output that is inverted to produce the AND result.
This topology has a disadvantage in that the logic gates that use it are slow. As terms are added to the equations, transistors are added to the ladder. The resistance of the ladder controls the rate at which the voltage at the top of the ladder may be discharged when the ladder turns on, and therefore large transistor sizes are needed to achieve faster switching times. Also, using larger area raises the gate capacitance which may remove any benefit from the increased area of the transistors, since the input signals will be delayed by the effect of increased capacitance.
Alternative topologies, known in the art, are the wide OR and deep AND topologies. The wide OR, shown in FIG. 1C, evaluates an OR equation by a drain-parallel connection of N-channel transistors coupled each to a logic input with their sources connected to ground. If any of the inputs are high, the individual transistors connected to them will conduct, pulling the node of parallel connection low. This signal can then be inverted to produce an OR output. For the deep AND, shown in FIG. 1D, a source-parallel connection of P-channel transistors with gates connected each to a logic input and their drains connected to a power signal is constructed. If any of the inputs are low, those transistors connected to those inputs will conduct, pulling the node of parallel connection high. This connection can then be inverted to produce an AND output.
A limitation of the wide OR and deep AND topologies is that a pullup (in the case of the wide OR) or pulldown (in the case of deep AND) circuit must be present for the node to be set to a proper voltage level when all of the input transistors are not conducting. (Without a pullup or pulldown, the node of parallel connection would be in a high impedance state when all transistors are off.) This pullup or pulldown is typically provided by a transistor. For the wide OR topology and deep AND technology, the pullup is usually a P-channel transistor connected to a power signal, sized to limit the current consumed when the summing node is pulled low.
The pullup or pulldown transistor must be appropriately sized so that when the logic circuit goes from a state in which all transistors are off to a state in which at least one transistor is on, the voltage at the node of parallel connection is quickly changed to the appropriate rail. Disadvantageously, the faster this change is made (due to a larger-sized pullup or pulldown), the more current is drawn through the logic gate when at least one of the transistors is held in the conducting state. For these topologies, evaluation speed and power consumption are a design tradeoff.
It would therefore be desirable to improve these and other topologies so that evaluation speed can be increased without a concomitant increase in power consumption.